OpenPET v2.0 Release Notes

What’s New

Firmware

  • Complete rewrite from scratch.
  • All code is revision controlled and reviewed in Bitbucket.
  • Unified architecture for all FPGAs and boards.
  • Minimal NIOS II Microprocessor on all FPGAs.
  • Standard 32-bit SPI bus for inter-module communication. A OSI model like architecture is used.
  • New clocking scheme on all FPGAs. e.g. Single PLL based clocking on all FPGAs with global reset in all modules.
  • Reusable and modular building blocks on all FPGAs. e.g. SoftwareFirmware Interface module, Cross Clock Domain modules, Processing Unit module, etc.
  • Utilize Double-Data-Rate high-speed communication for data path through backplane.
  • Generic command path design. e.g., allow an arbitrary command length instead of 80-bits.
  • Data is pushed from the lowest child to uppermost parent. Uppermost parent can throttle the speed of the acquisition based on the medium used, i.e., QuickUSB or Ethernet.
  • Multistage synchronizers to streamline clock-domain-crossing between different boards, FPGAs, and components.
  • New Software-Firmware Interface to allow simple SPI Master/Slave communications.
  • SPI interface is based on Altera’s standard SPI core.
  • Simplified directory structure and file names.
  • Renamed FPGA IOs to have descriptive names.
  • All firmware modules are organized for readability and flexibility. e.g. no stray code.
  • New Generic SRAM interface.
  • Firmware image creation is automated.
  • LEDs are now properly connected.
  • All modules use the rising edge of the clock, with global reset logic.
  • Slice is a clock (not a pulse) with a period of 8 System Clock cycles or 16.
  • New commands. Previous commands are no longer valid and should not be used.
  • New modes: IDLE, SCOPE, and SINGLES. In IDLE mode, the firmware does nothing. In SCOPE mode the firmware collects raw ADC data and saves it on external storage e.g. Workstation. In SINGLES mode the firmware processes the raw ADC data (current SINGLES example computes the energy i.e., area under the curve) and saves it on an external storage e.g. Workstation.
  • New settings, each mode above has its own 32-bit settings.
  • New action, each mode above has its own 32-bit action. Currently there are three actions. RESET, RUN, and STOP.
  • Synopsys Design Constraint (SDC) files are extensively used to specify the timing and area constraints of the design.
  • No timing violations.
  • All code is written in VHDL 1993 standard. numeric_std vhdl package is used. No proprietary packages are used.
  • Simple statemachines for all Scope and Singles modes.

SupportBoard

  • Generic design. i.e. (a) compile time parameters to enable/disable components and modules e.g. g_en_osc_mode and g_en_sng_mode, (b) variable FIFO depths e.g. g_DATA_FIFO_DEPTH, different detector boards e.g. g_adc_channels, g_adc_number, and g_adc_resolution, (c) different slice widths e.g. g_slice_div, (d) optional debugging e.g. g_debug.
  • JTAG-UART is enabled to display debugging info for additional verbosity.
  • New QuickUSB interface which supports both Host Interface Boards and SupportBoard connectors.
  • Faster Scope mode push architecture.
  • Better timing and synchronization due to the use of PLL based clocking and resets. A single PLL clocks all parts of the OpenPET platform including the external QuickUSB module.
  • Unified code for IO FPGAs. Both FPGAs share the same code base now. No need for two separate projects.
  • Generic queuing algorithm is implemented (same code is used on main and io FPGAs). The queue lines up SCOPE mode data from multiple detector boards then sends them out to external storage and processing.
  • Generic arbitration code (same code is used on main and io FPGAs) for random and fair detector board selection. This is useful in SINGLES mode. Colliding Single Words are randomly selected using a true number generator (using ring oscillators) implemented in FPGA fabric.

DetectorBoard

  • An optional TDC core is included.
  • Default firmware image is now uncompressed to allow users to generate any firmware logic they desire without any size restirctions.
  • Generic ADC interface: (a) Supports multiple TI ADC chips and resolutions, (b) generic deserialization without the use of PLLs.
  • Better timing and synchronization due to the use of PLL based clocking and resets. A single PLL clocks all parts the detector board including the ADCs.
  • Optional debugging interface to all modules.
  • Generic FIFO depths that can be changed on compile time to increase/decrease number of raw samples.
  • Advanced Scope mode with multiple parameters like samples before trigger, trigger window, etc.
  • Singles mode with generic pipeline interface. Number of pipeline stages is configured at compile time. This allows us to parameterize the processing time for a user-defined singles event.
  • Firmware based thresholds for Scope mode.
  • Example Singles mode is included to show users how to compute pulse energies or area under the curve.

Embedded Software

  • Complete rewrite from scratch.
  • Standard 32-bit SPI interface across all FPGAs and boards. A OSI model like architecture is used. e.g. Point to point communication, broadcast communication, time-to-live, number of retries, timeout, etc. The communication protocol follows a request-response architecture.
  • Interrupt based handing for SPI commands, QuickUSB commands, Software-Firmware commands.
  • Asynchronous, i.e., non-blocking commands are implemented. Parent doesn’t wait for child to respond, it will poll the reply later on at its leisure.
  • BSPs are auto-generated at compile time. BSP settings are stored in TCL scripts.

SupportBoard

Main FPGA
  • Child FPGA images are now considered any compressed. This allows the embedded software to program any firmware image regardless of size.
  • Generic QuickUSB interface. Allows parameterization of OpenPET command length, time-to-live, timeout, etc.
  • Ethernet compatible code base.
  • UART-over-JTAG console for additional verbosity.
IO FPGAs
  • Embedded Software is embedded in firmware image (bitstream) at build time. Reduces the number of files to manage.
  • Simple design. Extremely small NIOS-II. Code size is 7KB.

DetectorBoard

  • Embedded Software is embedded in firmware image (bitstream) at build time. Reduces the number of files to manage.
  • Extremely small NIOS-II. Code size is 11KB.
  • New peripheral device drivers for ADC, DAC, and SRAM.
  • Direct access to all ADC and DAC registers.

Software

  • New cross-platform scripting interface. Supports Microsoft Windows, Mac OS X, and GNU/Linux.
  • New Python Library OpenPETlib.py for easy python scripting.
  • New openpet executable for Windows x64. Executable is basically openpet.py built with pyinstaller.
  • Example cross-platform scripts for Scope and Singles modes. Example plotting script plot.py for quick Scope mode plotting.
  • Python library utilizers multiprocessing and queuing to achieve maximum QuickUSB throughput regardless of storage speed.
  • Optional realtime user defined data processing.

Hardware

  • No changes.

Upgrading from Previous Releases of OpenPET

Migration guide here.